Phase locked loops (PLL) and delay locked loops (DLL) are widely used to control clock signals.
FIG. 1 is a block diagram of a conventional PLL 100. The PLL 100 includes a phase detector 110, a charge pump 120, a loop filter 130, and an oscillator 140. The PLL 100 generates an output clock signal MCLK by multiplying the frequency of an input clock signal CLK using the oscillator 140. The oscillator 140 has a ring oscillator structure in which the output clock signal MCLK, which is output from a plurality of inverters 141 through 143 connected in series, is fed back to the first inverter 141. The frequency of the output clock signal MCLK is determined by the voltage level of a control signal VCTL generated by the loop filter 130. The phase detector 110 detects the phase difference between the input clock signal CLK and the output clock signal MCLK. The charge pump 120 generates a current corresponding to the phase difference, and the loop filter 130 generates the control signal VCTL at a voltage level corresponding to the current generated by the charge pump 120.
FIG. 2 is a block diagram of a conventional delay locked loop (DLL) 200. The DLL 200 includes a phase detector 210, a charge pump 220, a loop filter 230, and a delay circuit 240. The DLL 200 generates a signal by delaying an input clock signal CLK for a predetermined time using the delay circuit 240. The delay circuit 240 uses a plurality of inverters 241 through 243, which are connected in series, as delayers, and generates an output clock signal DCLK by delaying the input clock signal CLK for a predetermined time. The predetermined time is determined by the voltage level of a delay control signal VCTL generated by the loop filter 230. The phase detector 210 detects the phase difference between the input clock signal CLK and the output clock signal DCLK. The charge pump 220 generates a current corresponding to the phase difference, and the loop filter 230 generates the delay control signal VCTL with the voltage level corresponding to the current generated by the charge pump 220.
The conventional PLL 100 may be relatively insensitive to external jitter since the input clock signal CLK is not input to the oscillator 140. However, accumulation of jitter generated inside the oscillator 140 may reduce or prevent the stable generation of output clock signal MCLK. The conventional DLL 200 also may be relatively insensitive to jitter generated inside the delay circuit 240 since the input clock signal CLK is input to the delay circuit 240. However, in this case, external jitter may not be filtered and may be completely delivered to the delay circuit 240.